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• #13275 fudi2002 veterán

  Új Válasz 2021-07-13 12:44:02 #13275

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  fudi2002

  veterán

  Érdekességképp:

  Here is a list of the reasons for all the errors in TM5 (in order):
  
  Error 0 refresh stable error = voltage cutoff choke
  
  Error 1 = Simple Test 16mb ~ can be voltage related, can be tRFC issues,
  tiny timeout issues for example tRRD_L looks like a bit awkward
  
  Error 2, 12 is a timeout issue, somewhere something ends too quickly or you lack voltage and cells are not recharged in time
  a sync issue with other words which's first culprit is voltage somewhere or resistance somewhere
  
  Error 3 & 4 by checking the MT.cfg - are MirrorMove errors
  That set shows tRFC 2 issues and this tRFC "auto predicted"? is wrong.
  tRFC is so far always even
  as tRFC stepping are 32,16,8,4,2,
  
  Error 5 then 6 is a timings missmatch between dimms (data mirror move)
  
  Error 6 is purely related to the IMC, be if procODT, CLDO_VDDP or vSOC
  ~ it translates to "i couldn't even start transfering data, i crashed"
  4- 6x error 6 result in full bluescreen
  
  Error 7, 11 are burst tests
  it will error out if if CAD_BUS is not optimalwill error out if tRFC is too lowmostly errors out only after time
  Error 9 burst test 4mb is a voltage stability issue
  If you've lowered tRP, increase vDimm a tiny bit
  If you've increased tRP to longer delay, decrease vDIMM +0.01, one tiny step
  
  Error 10 mostly affects the first 5 main timings
  - noticed it can be tRCDWR to RD. can be tRP too, but it also can be the last two tRDWR & tRDRD which don't play well with your main tRCDWR / RD
  
  Error 13 = Simple Test 64mb, timeout while transferring big data
  = full crash, nearly always related to voltage ~ as memory was not able to autocorrect it
  
  Error 14 we know is MirrorMove Omb, a timeout issue
  - it can error after the 2nd or 3rd pass if something is off my some ns and just "got lost"

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