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• #3467 Raymond félisten FireGL #3462

  Új Válasz 2007-12-08 20:24:14 #3467

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  Raymond

  félisten

  válasz FireGL #3462 üzenetére

  "Az alaplap gyártók az otthoni "virtualizáló" userek miatt adnak ki kikapcsolhatatlan patchet ? Látom elsőkézből informálódsz, hogy mi lesz a késöbbi bios-okban mert nyilvánvalóan mindenki virtualizálni fog otthon a mostanság megvett B2-es reviziós Phenomján."

  Latszik hogy te is elsokezbol informalodsz. A problem nem csak virtualizacio kozben johet elo hanem magas terhelesek alatt. Lasd:

  Erratum 298 will be described as follows: "The processor operation to change the accessed or dirty bits of a page translation table entry in the L2 from 0b to 1b may not be atomic. A small window of time exists where other cached operations may cause the stale page translation table entry to be installed in the L3 before the modified copy is returned to the L2. In addition, if a probe for this cache line occurs during this window of time, the processor may not set the accessed or dirty bit and may corrupt data for an unrelated cached operation. The system may experience a machine check event reporting an L3 protocol error has occurred. In this case, the MC4 status register (MSR 0000_0410) will be equal to B2000000_000B0C0F or BA000000_000B0C0F. The MC4 address register (MSR 0000_0412) will be equal to 26h."

  [link]

  "The specific circumstances that can lead to the data corruption and system hang are most likely to occur during periods of high utilization of all four CPU cores."

  "We would be intrigued to see some handicapping of the exact odds of a TLB erratum-induced system hang occurring during the life of an average PC, but such considerations probably aren't going to fly for most customers. Even if the erratum occurs very infrequently, no one wants the possibility of a system crash at the worst possible moment hanging over his head, and no one wants a "broken" chip. That's surely why AMD has directed motherboard makers to enable the workaround by default in their BIOSes, with no option to disable it, even though it slows performance."

  "...MSI was able to supply us with a BIOS for its K9A2 Platinum motherboard that includes the TLB erratum workaround. Thus, we tested with an earlier revision of the MSI board's BIOS (version VP.0B7) and with the newer, patched BIOS (version 1.21). Per AMD's guidance on this issue, MSI apparently did not include a menu option to disable the workaround. In fact, the BIOS doesn't look to offer any cosmetic indicator that the workaround is in place."

  [link]

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